The invention relates to a power transistor cell with a gate cell terminal and a gate conductor structure—connected to the gate cell terminal—with an electrode section—adjoining a gate dielectric—for controlling the power transistor cell, and also to a power transistor component with fusible link.
Power semiconductor components are constructed from a multiplicity of essentially identical transistor cells that are often connected in parallel in their tens of thousands in order to increase the current-carrying capacity of the power semiconductor component. In modern vertically patterned power semiconductor components, the gate electrode of a respective transistor cell is in this case provided in a trench introduced into a semiconductor substrate, so that the gate electrode can be used to control a vertical conductive channel between two source and drain terminal regions opposite one another at the semiconductor substrate. The gate electrodes of the transistor cells of a power semiconductor component, for instance of a vertical MOSFET (metal oxide semiconductor field effect transistor) or of an IGBT (insulated gate bipolar transistor), are connected in parallel.
The functionality of the power semiconductor component is generally ensured only when the gate dielectric of all the transistor cells of a power semiconductor component is functionally capable. A short circuit between the gate electrode and the source or drain region of a transistor cell leads to the failure of the entire power semiconductor component. Since a plurality of power semiconductor components are connected in parallel as so-called power modules within a module housing, the requirements made of the reliability of the design of the gate dielectric multiply.
A single defect in the gate dielectric may lead to the failure of the component either at the end of production or after a relatively long operating time of the power semiconductor component.
In order to keep down the more critical failures during application operation of the power semiconductor components, the power semiconductor components are subjected to a stress test in the course of which the quality or defectiveness of the component is tested. For this purpose, generally at the wafer level, a stress voltage that is significantly increased compared with the operating voltages is applied between the gate electrode and the source or drain terminal in order to cause transistor cells with a defective gate dielectric to fail as early as in the test bed. The magnitude of the stress voltage is limited by the intrinsic breakdown voltage of the gate dielectric since, above the intrinsic breakdown voltage, charges are impressed into the gate dielectric and in turn reduce the service life of the gate dielectric.
Furthermore, it is known that power semiconductor components from wafers or from batches of wafers for which a broad distribution band of the breakdown voltage is determined tend toward early failures during application operation with a higher probability than power semiconductor components from wafers or from batches with a narrow distribution band of the breakdown voltage. In order to preclude as far as possible early failures during application operation, such wafers or else batches of such wafers are completely rejected. The production yield is thereby significantly reduced.
Moreover, complicated examinations in respect of the actual formation of the gate dielectric in the form of spot checks within a monitoring are necessary since the density of defects (defect density) in the gate dielectric cannot necessarily be deduced from the result of the stress test.
Therefore, various approaches are known for increasing the yield of power semiconductor components produced without any defects by subsequently disconnecting defective memory cells.
For instance, it is known to group transistor cells of MOS power field effect transistors into cell blocks and to test the cells or else cell blocks individually. In a subsequent process, only those cell blocks which have proved to be free of defects in the test are connected to the source terminal or to the drain terminal of the power semiconductor component.
U.S. Pat. No. 5,021,861 discloses a cell concept for power semiconductor components in which a fusible link is provided between the gate terminal of the power semiconductor component and the gate terminal of each cell block. In this case, the fusible link is designed in such a way that a short circuit in the cell block leads to the fusing of the fusible link. Any cell block that has one or a plurality of defective cells is isolated by interrupting the connection between the gate terminal of the cell block and the gate terminal of the power semiconductor component.
What is disadvantageous about this concept is the lack of sensitivity of the fusible link since, on the one hand, even very small gate leakage currents indicate a defective transistor cell, and, on the other hand, the fusible link must be robust enough to take up the permissible gate current of all the cells that are connected in parallel in the cell block.
U.S. Pat. No. 5,446,310 therefore proposes, in a first step, determining the current consumption at the gate electrode of individual cell blocks and, in a second step, by means of an external current source, fusing corresponding fusible links assigned to the cell blocks in a manner dependent on the previous test result.
In this case, firstly the increased outlay in the test bed is disadvantageous, as is the fact that the fusible links can only be fused in the test bed, but not in the finished, housed component. Furthermore, through the uncoupling of entire cell blocks, the current-carrying capacity of the power semiconductor component is significantly reduced and the loading on the remaining cell blocks is increased. Through the assignment of a respective fusible link to a plurality of transistor cells grouped in a cell block, generally not only the defective transistor cell itself but also a series of inherently functionally capable transistor cells are uncoupled and the current-carrying capacity of the power semiconductor component is reduced to a greater extent than is necessary.
Therefore, the invention is based on the object of providing a transistor cell and a power transistor component with high reliability for which a high yield is ensured in production.